The present invention relates generally to an electrostatic breakdown prevention circuit for a semiconductor device, and more particularly, to an electrostatic breakdown prevention circuit using a MOS transistor.
Conventionally, an electrostatic breakdown prevention circuit using a MOS transistor is widely utilized. Its basic structure is generally such that an NMOS transistor is connected on the side of, normally, VSS so as to be connected in parallel with an input terminal. FIG. 4(a) shows an example of an electrostatic breakdown prevention circuit connected with VSS 200. In this case, when electrostatic stress is applied to an input terminal 202, avalanche breakdown is caused at a drain terminal of an NMOS transistor 201 connected to an input terminal of an internal circuit 203, and due to a so-called snap-back phenomenon, a parasitic bipolar transistor formed of a source, a substrate, and a drain, as shown in FIG. 4(b) is turned on. This has a protecting effect, and thus, functions as an electrostatic breakdown prevention circuit.
When a semiconductor device including an internal circuit is manufactured, N type polysilicon with phosphorus as the impurity is normally used as a gate electrode of the above-mentioned NMOS transistor. Since current driveability at a certain level is required, a channel (W) length has to be several hundreds of xcexcm.
However, particularly in the case where the semiconductor device is intended to have low power consumption, an off-leak current in a subthreshold region generated in the NMOS transistor of the electrostatic breakdown prevention circuit is a cause of an increase in the standby current of the semiconductor device. In other words, operation at a lower voltage is required to attain a lower power consumption. However, in order to attain this, the threshold voltage of a MOS transistor forming the semiconductor device has to be set at a lower level. If the threshold voltage of the NMOS transistor forming the electrostatic breakdown prevention circuit is lowered similarly, together with the large W length, this leads to a remarkable increase in the leak current. Since the threshold voltage of the NMOS transistor forming the electrostatic breakdown prevention circuit does not have direct influence on the operation of the semiconductor device, the problem is solved by setting the threshold voltage of the NMOS transistor higher than that of the MOS transistor forming the semiconductor device. However, additional photolithography processes are necessary for this, which results in an increase in the number of processes.
Means adopted by an electrostatic breakdown prevention circuit for a semiconductor device according to the present invention in order to attain the above-mentioned object is to provide a P type gate for an NMOS transistor forming the electrostatic breakdown prevention circuit. This structure utilizes the energy gap in the gate electrode to increase its threshold voltage by about 1.1V higher than the threshold voltage in the case where the gate were of the N type.